Modernly, turn-on and bring-up of a commonplace electronic device such as a computer is complex, far more so than was the case in earlier generations of commonly available computers. Much of the complexity is hidden from the causal user and from a majority of software developers.
During early computer start-up the main semiconductor memory is typically not available, and a cache memory (which may be on or off the CPU (Central Processor Unit)) chip(s) is used by firmware as general purpose memory (e.g. for stack) in order execute instruction codes to determine the presence and characteristics of any RAM (Random Access Memory) present. This is commonly performed by means of a dialog on an I2C (Inter-Integrated Circuit) which is a slow, multi-master serial computer bus. This is an early part of a complex many-stage process by which a computer pulls itself up by its (metaphorical) bootstraps, commonly referred to simply as booting. Having located any RAM present the RAM can be configured in and the loading process may advance to a next step and, in due course, to a POST (Power-On Self Test).
SMBus (System Management Bus) is a two-signal bus, a subset of I2C and used for communication with low-bandwidth devices on a motherboard, especially power-related chips such as a laptop rechargeable battery subsystem. One purpose of deploying SMBus is to promote robustness with interoperability.
I2C and/or SMBus have been proposed for communication between a debugging station (host) and a target. Inter alia, so doing avoids problems of using communications facilities which may be so rich as to preclude simple code support within the target device and/or which may be trampled on by software loaded later in a typical booting process. Such an arrangement might be needed, for example, for debugging a POST (Power-On Self Test) firmware routine however there are disadvantages pursuant to using I2C and/or SMBus in this way. Such previously developed solutions may, for example, adversely interact with the very I2C circuits that comprise the test-target feature within the code under test. Also SMBus requires at least two wires (in addition to reference ground); one each for clock and for data. The term “wire” is used (herein) as commonly understood in the well-known VHDL (very high speed integrated circuit hardware definition language) arts and does not necessary refer to a cabled metallic conductor.
Single-wire UART (Universal Asynchronous Receiver-Transmitter) has also been used for communications where performance criteria are relatively modest, including debugging station connection. Single wire UART is well-known in the art but, as compared with single-wire UART, embodiments of the invention offer at least two significant advantages: firstly a single master, multiple slaves multipoint communications topology may be used. Previously developed solutions using single-wire UART have provided point-to-point communication. Secondly, the communication speed and protocol can be readily be adjusted by firmware and/or software adjustable settings. Single-wire UART implementations are lack sufficient flexibility in that regard, in part because of standards constraints.
In summary, single-wire GPIO communication has the advantages as I2C, and has the low cost as single-wire UART.
The present invention may overcome certain disadvantages of using resources visible to OS (operating system) and also the disadvantages of using SMBus for debugging communication. At the same time it can be more cost effective than more traditional previously developed solutions such as ICE (In-circuit Emulation). That is not to suggest that the only problem with using ICE and the like is the cost thereof.
Thus, the disclosed improved computer designs include embodiments of the present invention enable superior tradeoffs in regards to the problems and shortcomings outlined above, and more.